The present invention relates to a synchronous DRAM that performs data input/output in sync with a clock and that has initial mode setting circuit.
With the increase in the system clock frequency of microprocessors, demand has risen for DRAM with which high-speed access is possible. In response to this demand, synchronous DRAMs have been developed.
A synchronous DRAM is provided with a mode register and by setting the burst length, wrap type and CAS latency in the register, optimal operation for the system can be achieved.
The burst length referred to here is the number of data that are input/output continuously and it can be set to 1, 2, 4, 8 or full page. Wrap type refers to the method with which column addresses which are internally generated are changed at the time of burst access. The sequential method, that changes column addresses continuously within the same bank, or the interleave method, that scrambles column addresses alternately between two banks can be selected for the wrap type. CAS latency refers to the number of clock cycles that pass after the read command is input until the time when the first data are read, and a latency of 1, 2 or 3 can be selected.
FIG. 4 is a simplified illustration of a circuit in the prior art that is related to mode setting within a synchronous DRAM.
The mode register 10 is provided with 3-bit D flip flops 11 to 13. The outputs from the D flip flops 11, 12 and 13 respectively indicate the burst length, wrap type and CAS latency. FIG. 4 is simplified, but in fact, one flip flop is provided for each of the 1, 2, 4, 8 and full page burst lengths and this applies to other modes.
Each of the AND gates 21 to 23 is opened by the mode register setting signal MRS and their outputs are determined by the values of the 7-bit addresses A0 to A6. The mode register setting signal MRS is an output of the AND gate 25 and it is set to `1` when the chip select signal *CS, the row address strobe signal *RAS, the column address strobe signal *CAS and the write enable signal *WE are all set to `0`. Generally speaking, a signal *S means the signal whose logical value is in inverse relation to a signal S.
In the structure described above, with a program, by setting the chip select signal *CS, the row address strobe signal *RAS, the column address strobe signal *CAS and the write enable signal *WE to `0` for the synchronous DRAM, and at the same time, by assigning specific address values A0 to A6, the appropriate operation mode can be set in the mode register 10.
Generally, a DRAM cannot be accessed immediately after the power source voltage VCC starts up, as shown in FIG. 3A. Namely, after the power source voltage VCC reaches a specified value, such as 3.3 V.+-.0.3 V, 200 .mu.s, i.e., the time that is required for the substrate bias circuit within the DRAM to stabilize, is allowed to pass. Further, it is necessary to perform dummy operations for 8 cycles in order to set the potential of the sequential logic circuit to a normal level. In the case of synchronous DRAM, furthermore, one clock cycle for the mode setting described above and three clock cycles for awaiting stabilization of the voltage level of the signal related to the setting are required, so a total of 4 additional clock cycles is required.
Because of this, a long time must elapse after power up before access is enabled, and it is necessary to set the mode with an initialization routine or the like before the memory can be accessed after power up.